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<title>XSETBV—Set Extended Control Register </title></head>
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<h1>XSETBV—Set Extended Control Register</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>0F 01 D1</td>
<td>XSETBV</td>
<td>NP</td>
<td>Valid</td>
<td>Valid</td>
<td>Write the value in EDX:EAX to the XCR specified by ECX.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>NP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Writes the contents of registers EDX:EAX into the 64-bit extended control register (XCR) specified in the ECX register. (On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of the EDX register are copied to high-order 32 bits of the selected XCR and the contents of the EAX register are copied to low-order 32 bits of the XCR. (On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an XCR should be set to values previously read.</p>
<p>This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) is generated. Specifying a reserved or unimplemented XCR in ECX will also cause a general protection exception. The processor will also generate a general protection exception if software attempts to write to reserved bits in an XCR.</p>
<p>Currently, only XCR0 is supported. Thus, all other values of ECX are reserved and will cause a #GP(0). Note that bit 0 of XCR0 (corresponding to x87 state) must be set to 1; the instruction will cause a #GP(0) if an attempt is made to clear this bit. In addition, the instruction causes a #GP(0) if an attempt is made to set XCR0[2] (AVX state) while clearing XCR0[1] (SSE state); it is necessary to set both bits to use AVX instructions; Section 13.3, “Enabling the XSAVE Feature Set and XSAVE-Enabled Features,” of <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>.</p>
<h2>Operation</h2>
<pre>XCR[ECX] ← EDX:EAX;</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>XSETBV:</p>
<p>void _xsetbv( unsigned int, unsigned __int64);</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>
<p>If the current privilege level is not 0.</p>
<p>If an invalid XCR is specified in ECX.</p>
<p>If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.</p>
<p>If an attempt is made to clear bit 0 of XCR0.</p>
<p>If an attempt is made to set XCR0[2:1] to 10b.</p></td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</p>
<p>If CR4.OSXSAVE[bit 18] = 0.</p>
<p>If the LOCK prefix is used.</p>
<p>If 66H, F3H or F2H prefix is used.</p></td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP</td>
<td>
<p>If an invalid XCR is specified in ECX.</p>
<p>If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX.</p>
<p>If an attempt is made to clear bit 0 of XCR0.</p>
<p>If an attempt is made to set XCR0[2:1] to 10b.</p></td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.01H:ECX.XSAVE[bit 26] = 0.</p>
<p>If CR4.OSXSAVE[bit 18] = 0.</p>
<p>If the LOCK prefix is used.</p>
<p>If 66H, F3H or F2H prefix is used.</p></td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>The XSETBV instruction is not recognized in virtual-8086 mode.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p></body></html>